src/core_cm0.h
説明を見る。
00001 /**************************************************************************/
00024 #ifndef __CM0_CORE_H__
00025 #define __CM0_CORE_H__
00026 
00045 #ifdef __cplusplus
00046  extern "C" {
00047 #endif 
00048 
00049 #define __CM0_CMSIS_VERSION_MAIN  (0x01)                                                       
00050 #define __CM0_CMSIS_VERSION_SUB   (0x30)                                                       
00051 #define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) 
00053 #define __CORTEX_M                (0x00)                                                       
00055 #include <stdint.h>                           /* Include standard types */
00056 
00057 #if defined (__ICCARM__)
00058   #include <intrinsics.h>                     /* IAR Intrinsics   */
00059 #endif
00060 
00061 
00062 #ifndef __NVIC_PRIO_BITS
00063   #define __NVIC_PRIO_BITS    2               
00064 #endif
00065 
00066 
00067 
00068 
00075 #ifdef __cplusplus
00076   #define     __I     volatile                
00077 #else
00078   #define     __I     volatile const          
00079 #endif
00080 #define     __O     volatile                  
00081 #define     __IO    volatile                  
00085 /*******************************************************************************
00086  *                 Register Abstraction
00087  ******************************************************************************/
00088 
00097 typedef struct
00098 {
00099   __IO uint32_t ISER[1];                      
00100        uint32_t RESERVED0[31];
00101   __IO uint32_t ICER[1];                      
00102        uint32_t RSERVED1[31];
00103   __IO uint32_t ISPR[1];                      
00104        uint32_t RESERVED2[31];
00105   __IO uint32_t ICPR[1];                      
00106        uint32_t RESERVED3[31];
00107        uint32_t RESERVED4[64];
00108   __IO uint32_t IPR[8];                       
00109 }  NVIC_Type; /* end of group CMSIS_CM0_NVIC */
00111 
00112 
00117 typedef struct
00118 {
00119   __I  uint32_t CPUID;                        
00120   __IO uint32_t ICSR;                         
00121        uint32_t RESERVED0;                                      
00122   __IO uint32_t AIRCR;                        
00123   __IO uint32_t SCR;                          
00124   __IO uint32_t CCR;                          
00125        uint32_t RESERVED1;                                      
00126   __IO uint32_t SHP[2];                       
00127   __IO uint32_t SHCSR;                        
00128        uint32_t RESERVED2[2];                                   
00129   __IO uint32_t DFSR;                         
00130 } SCB_Type;                                                
00131 
00132 /* SCB CPUID Register Definitions */
00133 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             
00134 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          
00136 #define SCB_CPUID_VARIANT_Pos              20                                             
00137 #define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               
00139 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             
00140 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFul << SCB_CPUID_ARCHITECTURE_Pos)          
00142 #define SCB_CPUID_PARTNO_Pos                4                                             
00143 #define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              
00145 #define SCB_CPUID_REVISION_Pos              0                                             
00146 #define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              
00148 /* SCB Interrupt Control State Register Definitions */
00149 #define SCB_ICSR_NMIPENDSET_Pos            31                                             
00150 #define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               
00152 #define SCB_ICSR_PENDSVSET_Pos             28                                             
00153 #define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                
00155 #define SCB_ICSR_PENDSVCLR_Pos             27                                             
00156 #define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                
00158 #define SCB_ICSR_PENDSTSET_Pos             26                                             
00159 #define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                
00161 #define SCB_ICSR_PENDSTCLR_Pos             25                                             
00162 #define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                
00164 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             
00165 #define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               
00167 #define SCB_ICSR_ISRPENDING_Pos            22                                             
00168 #define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               
00170 #define SCB_ICSR_VECTPENDING_Pos           12                                             
00171 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          
00173 #define SCB_ICSR_VECTACTIVE_Pos             0                                             
00174 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           
00176 /* SCB Application Interrupt and Reset Control Register Definitions */
00177 #define SCB_AIRCR_VECTKEY_Pos              16                                             
00178 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            
00180 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             
00181 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        
00183 #define SCB_AIRCR_ENDIANESS_Pos            15                                             
00184 #define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               
00186 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             
00187 #define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             
00189 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             
00190 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           
00192 /* SCB System Control Register Definitions */
00193 #define SCB_SCR_SEVONPEND_Pos               4                                             
00194 #define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 
00196 #define SCB_SCR_SLEEPDEEP_Pos               2                                             
00197 #define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 
00199 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             
00200 #define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               
00202 /* SCB Configuration Control Register Definitions */
00203 #define SCB_CCR_STKALIGN_Pos                9                                             
00204 #define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  
00206 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             
00207 #define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               
00209 /* SCB System Handler Control and State Register Definitions */
00210 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             
00211 #define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            
00213 /* SCB Debug Fault Status Register Definitions */
00214 #define SCB_DFSR_EXTERNAL_Pos               4                                             
00215 #define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 
00217 #define SCB_DFSR_VCATCH_Pos                 3                                             
00218 #define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   
00220 #define SCB_DFSR_DWTTRAP_Pos                2                                             
00221 #define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  
00223 #define SCB_DFSR_BKPT_Pos                   1                                             
00224 #define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     
00226 #define SCB_DFSR_HALTED_Pos                 0                                             
00227 #define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   
00228  /* end of group CMSIS_CM0_SCB */
00229 
00230 
00235 typedef struct
00236 {
00237   __IO uint32_t CTRL;                         
00238   __IO uint32_t LOAD;                         
00239   __IO uint32_t VAL;                          
00240   __I  uint32_t CALIB;                        
00241 } SysTick_Type;
00242 
00243 /* SysTick Control / Status Register Definitions */
00244 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             
00245 #define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            
00247 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             
00248 #define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            
00250 #define SysTick_CTRL_TICKINT_Pos            1                                             
00251 #define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              
00253 #define SysTick_CTRL_ENABLE_Pos             0                                             
00254 #define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               
00256 /* SysTick Reload Register Definitions */
00257 #define SysTick_LOAD_RELOAD_Pos             0                                             
00258 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        
00260 /* SysTick Current Register Definitions */
00261 #define SysTick_VAL_CURRENT_Pos             0                                             
00262 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        
00264 /* SysTick Calibration Register Definitions */
00265 #define SysTick_CALIB_NOREF_Pos            31                                             
00266 #define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               
00268 #define SysTick_CALIB_SKEW_Pos             30                                             
00269 #define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                
00271 #define SysTick_CALIB_TENMS_Pos             0                                             
00272 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        
00273  /* end of group CMSIS_CM0_SysTick */
00274 
00275 
00280 typedef struct
00281 {
00282   __IO uint32_t DHCSR;                        
00283   __O  uint32_t DCRSR;                        
00284   __IO uint32_t DCRDR;                        
00285   __IO uint32_t DEMCR;                        
00286 } CoreDebug_Type;
00287 
00288 /* Debug Halting Control and Status Register */
00289 #define CoreDebug_DHCSR_DBGKEY_Pos         16                                             
00290 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       
00292 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             
00293 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        
00295 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             
00296 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       
00298 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             
00299 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          
00301 #define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             
00302 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           
00304 #define CoreDebug_DHCSR_S_HALT_Pos         17                                             
00305 #define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            
00307 #define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             
00308 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          
00310 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             
00311 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        
00313 #define CoreDebug_DHCSR_C_STEP_Pos          2                                             
00314 #define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            
00316 #define CoreDebug_DHCSR_C_HALT_Pos          1                                             
00317 #define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            
00319 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             
00320 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         
00322 /* Debug Core Register Selector Register */
00323 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             
00324 #define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            
00326 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             
00327 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         
00329 /* Debug Exception and Monitor Control Register */
00330 #define CoreDebug_DEMCR_DWTENA_Pos         24                                             
00331 #define CoreDebug_DEMCR_DWTENA_Msk         (1ul << CoreDebug_DEMCR_DWTENA_Pos)            
00333 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             
00334 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        
00336 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             
00337 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      
00338  /* end of group CMSIS_CM0_CoreDebug */
00339 
00340 
00341 /* Memory mapping of Cortex-M0 Hardware */
00342 #define SCS_BASE            (0xE000E000)                              
00343 #define CoreDebug_BASE      (0xE000EDF0)                              
00344 #define SysTick_BASE        (SCS_BASE +  0x0010)                      
00345 #define NVIC_BASE           (SCS_BASE +  0x0100)                      
00346 #define SCB_BASE            (SCS_BASE +  0x0D00)                      
00348 #define SCB                 ((SCB_Type *)           SCB_BASE)         
00349 #define SysTick             ((SysTick_Type *)       SysTick_BASE)     
00350 #define NVIC                ((NVIC_Type *)          NVIC_BASE)        
00351 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   
00353  /* end of group CMSIS_CM0_core_register */
00354 
00355 
00356 /*******************************************************************************
00357  *                Hardware Abstraction Layer
00358  ******************************************************************************/
00359 
00360 #if defined ( __CC_ARM   )
00361   #define __ASM            __asm                                      
00362   #define __INLINE         __inline                                   
00364 #elif defined ( __ICCARM__ )
00365   #define __ASM           __asm                                       
00366   #define __INLINE        inline                                      
00368 #elif defined   (  __GNUC__  )
00369   #define __ASM            __asm                                      
00370   #define __INLINE         inline                                     
00372 #elif defined   (  __TASKING__  )
00373   #define __ASM            __asm                                      
00374   #define __INLINE         inline                                     
00376 #endif
00377 
00378 
00379 /* ###################  Compiler specific Intrinsics  ########################### */
00380 
00381 #if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
00382 /* ARM armcc specific functions */
00383 
00384 #define __enable_fault_irq                __enable_fiq
00385 #define __disable_fault_irq               __disable_fiq
00386 
00387 #define __NOP                             __nop
00388 #define __WFI                             __wfi
00389 #define __WFE                             __wfe
00390 #define __SEV                             __sev
00391 #define __ISB()                           __isb(0)
00392 #define __DSB()                           __dsb(0)
00393 #define __DMB()                           __dmb(0)
00394 #define __REV                             __rev
00395 
00396 
00397 /* intrinsic void __enable_irq();     */
00398 /* intrinsic void __disable_irq();    */
00399 
00400 
00408 extern uint32_t __get_PSP(void);
00409 
00418 extern void __set_PSP(uint32_t topOfProcStack);
00419 
00428 extern uint32_t __get_MSP(void);
00429 
00438 extern void __set_MSP(uint32_t topOfMainStack);
00439 
00448 extern uint32_t __REV16(uint16_t value);
00449 
00458 extern int32_t __REVSH(int16_t value);
00459 
00460 
00461 #if (__ARMCC_VERSION < 400000)
00462 
00470 extern uint32_t __get_PRIMASK(void);
00471 
00479 extern void __set_PRIMASK(uint32_t priMask);
00480 
00488 extern uint32_t __get_CONTROL(void);
00489 
00497 extern void __set_CONTROL(uint32_t control);
00498 
00499 #else  /* (__ARMCC_VERSION >= 400000)  */
00500 
00501 
00509 static __INLINE uint32_t __get_PRIMASK(void)
00510 {
00511   register uint32_t __regPriMask         __ASM("primask");
00512   return(__regPriMask);
00513 }
00514 
00522 static __INLINE void __set_PRIMASK(uint32_t priMask)
00523 {
00524   register uint32_t __regPriMask         __ASM("primask");
00525   __regPriMask = (priMask);
00526 }
00527 
00535 static __INLINE uint32_t __get_CONTROL(void)
00536 {
00537   register uint32_t __regControl         __ASM("control");
00538   return(__regControl);
00539 }
00540 
00548 static __INLINE void __set_CONTROL(uint32_t control)
00549 {
00550   register uint32_t __regControl         __ASM("control");
00551   __regControl = control;
00552 }
00553 
00554 #endif /* __ARMCC_VERSION  */ 
00555 
00556 
00557 
00558 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
00559 /* IAR iccarm specific functions */
00560 
00561 #define __enable_irq                              __enable_interrupt        
00562 #define __disable_irq                             __disable_interrupt       
00564 static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
00565 static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
00566 
00567 #define __NOP                                     __no_operation            
00568 static __INLINE  void __WFI()                     { __ASM ("wfi"); }
00569 static __INLINE  void __WFE()                     { __ASM ("wfe"); }
00570 static __INLINE  void __SEV()                     { __ASM ("sev"); }
00571 
00572 /* intrinsic void __ISB(void)                                     */
00573 /* intrinsic void __DSB(void)                                     */
00574 /* intrinsic void __DMB(void)                                     */
00575 /* intrinsic void __set_PRIMASK();                                */
00576 /* intrinsic void __get_PRIMASK();                                */
00577 
00578 
00579 /* intrinsic uint32_t __REV(uint32_t value);                      */
00580 /* intrinsic uint32_t __REVSH(uint32_t value);                    */
00581 
00582 
00590 extern uint32_t __get_PSP(void);
00591 
00600 extern void __set_PSP(uint32_t topOfProcStack);
00601 
00610 extern uint32_t __get_MSP(void);
00611 
00620 extern void __set_MSP(uint32_t topOfMainStack);
00621 
00630 extern uint32_t __REV16(uint16_t value);
00631 
00632 
00633 
00634 
00635 
00636 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
00637 /* GNU gcc specific functions */
00638 
00639 static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
00640 static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
00641 
00642 static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
00643 static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
00644 
00645 static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
00646 static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
00647 static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
00648 static __INLINE void __SEV()                      { __ASM volatile ("sev"); }
00649 static __INLINE void __ISB()                      { __ASM volatile ("isb"); }
00650 static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }
00651 static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }
00652 
00653 
00661 extern uint32_t __get_PSP(void);
00662 
00671 extern void __set_PSP(uint32_t topOfProcStack);
00672 
00681 extern uint32_t __get_MSP(void);
00682 
00691 extern void __set_MSP(uint32_t topOfMainStack);
00692 
00700 extern uint32_t  __get_PRIMASK(void);
00701 
00709 extern void __set_PRIMASK(uint32_t priMask);
00710 
00718 extern uint32_t __get_CONTROL(void);
00719 
00727 extern void __set_CONTROL(uint32_t control);
00728 
00737 extern uint32_t __REV(uint32_t value);
00738 
00747 extern uint32_t __REV16(uint16_t value);
00748 
00757 extern int32_t __REVSH(int16_t value);
00758 
00759 
00760 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
00761 /* TASKING carm specific functions */
00762 
00763 /*
00764  * The CMSIS functions have been implemented as intrinsics in the compiler.
00765  * Please use "carm -?i" to get an up to date list of all instrinsics,
00766  * Including the CMSIS ones.
00767  */
00768 
00769 #endif
00770 
00771 
00779 
00780 /* ##########################   NVIC functions  #################################### */
00781 
00782 /* Interrupt Priorities are WORD accessible only under ARMv6M                   */
00783 /* The following MACROS handle generation of the register offset and byte masks */
00784 #define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
00785 #define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
00786 #define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
00787 
00788 
00797 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
00798 {
00799   NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
00800 }
00801 
00810 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
00811 {
00812   NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
00813 }
00814 
00824 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
00825 {
00826   return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
00827 }
00828 
00837 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
00838 {
00839   NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
00840 }
00841 
00850 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00851 {
00852   NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
00853 }
00854 
00867 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
00868 {
00869   if(IRQn < 0) {
00870     SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 
00871         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
00872   else {
00873     NVIC->IPR[_IP_IDX(IRQn)] = (NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
00874         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
00875 }
00876 
00892 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
00893 {
00894 
00895   if(IRQn < 0) {
00896     return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
00897   else {
00898     return((uint32_t)((NVIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
00899 }
00900 
00901 
00902 
00903 /* ##################################    SysTick function  ############################################ */
00904 
00905 #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
00906 
00917 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
00918 { 
00919   if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
00920                                                                
00921   SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
00922   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
00923   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
00924   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
00925                    SysTick_CTRL_TICKINT_Msk   | 
00926                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
00927   return (0);                                                  /* Function successful */
00928 }
00929 
00930 #endif
00931 
00932 
00933 
00934 
00935 /* ##################################    Reset function  ############################################ */
00936 
00942 static __INLINE void NVIC_SystemReset(void)
00943 {
00944   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
00945                  SCB_AIRCR_SYSRESETREQ_Msk);
00946   __DSB();                                                                             /* Ensure completion of memory access */              
00947   while(1);                                                                            /* wait until reset */
00948 }
00949  /* end of group CMSIS_CM0_Core_FunctionInterface */
00951 
00952 #ifdef __cplusplus
00953 }
00954 #endif
00955  /* end of group CMSIS_CM0_core_definitions */
00957 
00958 #endif /* __CM0_CORE_H__ */
00959 
00960 /*lint -restore */
 全て クラス ファイル 関数 変数 列挙型 列挙型の値 マクロ定義