CMSIS Cortex-M0 Core Peripheral Access Layer Header File. [詳細]
#include <stdint.h>
構成 | |
struct | NVIC_Type |
struct | SCB_Type |
struct | SysTick_Type |
struct | CoreDebug_Type |
マクロ定義 | |
#define | __CM0_CMSIS_VERSION_MAIN (0x01) |
#define | __CM0_CMSIS_VERSION_SUB (0x30) |
#define | __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) |
#define | __CORTEX_M (0x00) |
#define | __NVIC_PRIO_BITS 2 |
#define | __I volatile const |
#define | __O volatile |
#define | __IO volatile |
#define | SCB_CPUID_IMPLEMENTER_Pos 24 |
#define | SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) |
#define | SCB_CPUID_VARIANT_Pos 20 |
#define | SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) |
#define | SCB_CPUID_ARCHITECTURE_Pos 16 |
#define | SCB_CPUID_ARCHITECTURE_Msk (0xFul << SCB_CPUID_ARCHITECTURE_Pos) |
#define | SCB_CPUID_PARTNO_Pos 4 |
#define | SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) |
#define | SCB_CPUID_REVISION_Pos 0 |
#define | SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) |
#define | SCB_ICSR_NMIPENDSET_Pos 31 |
#define | SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) |
#define | SCB_ICSR_PENDSVSET_Pos 28 |
#define | SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) |
#define | SCB_ICSR_PENDSVCLR_Pos 27 |
#define | SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) |
#define | SCB_ICSR_PENDSTSET_Pos 26 |
#define | SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) |
#define | SCB_ICSR_PENDSTCLR_Pos 25 |
#define | SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) |
#define | SCB_ICSR_ISRPREEMPT_Pos 23 |
#define | SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) |
#define | SCB_ICSR_ISRPENDING_Pos 22 |
#define | SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) |
#define | SCB_ICSR_VECTPENDING_Pos 12 |
#define | SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) |
#define | SCB_ICSR_VECTACTIVE_Pos 0 |
#define | SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) |
#define | SCB_AIRCR_VECTKEY_Pos 16 |
#define | SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) |
#define | SCB_AIRCR_VECTKEYSTAT_Pos 16 |
#define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) |
#define | SCB_AIRCR_ENDIANESS_Pos 15 |
#define | SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) |
#define | SCB_AIRCR_SYSRESETREQ_Pos 2 |
#define | SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) |
#define | SCB_AIRCR_VECTCLRACTIVE_Pos 1 |
#define | SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) |
#define | SCB_SCR_SEVONPEND_Pos 4 |
#define | SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) |
#define | SCB_SCR_SLEEPDEEP_Pos 2 |
#define | SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) |
#define | SCB_SCR_SLEEPONEXIT_Pos 1 |
#define | SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) |
#define | SCB_CCR_STKALIGN_Pos 9 |
#define | SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) |
#define | SCB_CCR_UNALIGN_TRP_Pos 3 |
#define | SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) |
#define | SCB_SHCSR_SVCALLPENDED_Pos 15 |
#define | SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) |
#define | SCB_DFSR_EXTERNAL_Pos 4 |
#define | SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) |
#define | SCB_DFSR_VCATCH_Pos 3 |
#define | SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) |
#define | SCB_DFSR_DWTTRAP_Pos 2 |
#define | SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) |
#define | SCB_DFSR_BKPT_Pos 1 |
#define | SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) |
#define | SCB_DFSR_HALTED_Pos 0 |
#define | SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) |
#define | SysTick_CTRL_COUNTFLAG_Pos 16 |
#define | SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) |
#define | SysTick_CTRL_CLKSOURCE_Pos 2 |
#define | SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) |
#define | SysTick_CTRL_TICKINT_Pos 1 |
#define | SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) |
#define | SysTick_CTRL_ENABLE_Pos 0 |
#define | SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) |
#define | SysTick_LOAD_RELOAD_Pos 0 |
#define | SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) |
#define | SysTick_VAL_CURRENT_Pos 0 |
#define | SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) |
#define | SysTick_CALIB_NOREF_Pos 31 |
#define | SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) |
#define | SysTick_CALIB_SKEW_Pos 30 |
#define | SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) |
#define | SysTick_CALIB_TENMS_Pos 0 |
#define | SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) |
#define | CoreDebug_DHCSR_DBGKEY_Pos 16 |
#define | CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) |
#define | CoreDebug_DHCSR_S_RESET_ST_Pos 25 |
#define | CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) |
#define | CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 |
#define | CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
#define | CoreDebug_DHCSR_S_LOCKUP_Pos 19 |
#define | CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) |
#define | CoreDebug_DHCSR_S_SLEEP_Pos 18 |
#define | CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) |
#define | CoreDebug_DHCSR_S_HALT_Pos 17 |
#define | CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) |
#define | CoreDebug_DHCSR_S_REGRDY_Pos 16 |
#define | CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) |
#define | CoreDebug_DHCSR_C_MASKINTS_Pos 3 |
#define | CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) |
#define | CoreDebug_DHCSR_C_STEP_Pos 2 |
#define | CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) |
#define | CoreDebug_DHCSR_C_HALT_Pos 1 |
#define | CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) |
#define | CoreDebug_DHCSR_C_DEBUGEN_Pos 0 |
#define | CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) |
#define | CoreDebug_DCRSR_REGWnR_Pos 16 |
#define | CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) |
#define | CoreDebug_DCRSR_REGSEL_Pos 0 |
#define | CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) |
#define | CoreDebug_DEMCR_DWTENA_Pos 24 |
#define | CoreDebug_DEMCR_DWTENA_Msk (1ul << CoreDebug_DEMCR_DWTENA_Pos) |
#define | CoreDebug_DEMCR_VC_HARDERR_Pos 10 |
#define | CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) |
#define | CoreDebug_DEMCR_VC_CORERESET_Pos 0 |
#define | CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) |
#define | SCS_BASE (0xE000E000) |
#define | CoreDebug_BASE (0xE000EDF0) |
#define | SysTick_BASE (SCS_BASE + 0x0010) |
#define | NVIC_BASE (SCS_BASE + 0x0100) |
#define | SCB_BASE (SCS_BASE + 0x0D00) |
#define | SCB ((SCB_Type *) SCB_BASE) |
#define | SysTick ((SysTick_Type *) SysTick_BASE) |
#define | NVIC ((NVIC_Type *) NVIC_BASE) |
#define | CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) |
#define | _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) |
#define | _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) |
#define | _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) |
CMSIS Cortex-M0 Core Peripheral Access Layer Header File.