Public 変数 | |
union { | |
__I uint32_t RBR | |
__O uint32_t LPC_UART_TypeDef::THR | |
__IO uint32_t LPC_UART_TypeDef::DLL | |
}; | |
union { | |
__IO uint32_t DLM | |
__IO uint32_t LPC_UART_TypeDef::IER | |
}; | |
union { | |
__I uint32_t IIR | |
__O uint32_t LPC_UART_TypeDef::FCR | |
}; | |
__IO uint32_t | LCR |
__IO uint32_t | MCR |
__I uint32_t | LSR |
__I uint32_t | MSR |
__IO uint32_t | SCR |
__IO uint32_t | ACR |
uint32_t | RESERVED0 |
__IO uint32_t | FDR |
uint32_t | RESERVED1 |
__IO uint32_t | TER |
uint32_t | RESERVED2 [6] |
__IO uint32_t | RS485CTRL |
__IO uint32_t | ADRMATCH |
__IO uint32_t | RS485DLY |
__I uint32_t | FIFOLVL |
__IO uint32_t LPC_UART_TypeDef::DLM |
Offset: 0x004 Divisor Latch MSB (R/W)
__I uint32_t LPC_UART_TypeDef::IIR |
Offset: 0x008 Interrupt ID Register (R/ )
__I uint32_t LPC_UART_TypeDef::RBR |
Offset: 0x000 Receiver Buffer Register (R/ )